1. Field
Example embodiments relate to a semiconductor memory device, and more particularly to, a NOR flash memory device for reducing a fluctuation of a read voltage generated during a read while write (RWW) operation.
2. Description of the Related Art
Flash memories may be generally used as nonvolatile memory devices for electrically deleting or recording data and may need less power consumption than magnetic disc memory based storage media, which may have relatively fast access times comparable to hard discs.
Flash memory may be classified into one of NOR type flash memory and NAND type flash memory according to a connection of cells and bit lines. NOR type flash memory may have one bit line and two or more cell transistors connected in parallel, may store data using a channel hot electron method, and may erase data using a Fowler-Nordheim (F-N) tunneling method. NAND type flash memory may have one bit line and two or more cell transistors connected in series and may store and erase data using the F-N tunneling method. Although NOR type flash memory may be disadvantageous in highly integrated devices due to a relatively large amount of current consumption, NOR type flash memory may be advantageous to a high speed operation. Meanwhile, since NAND type flash memory may use less cell current than NOR type flash memory, NAND type flash memory may be advantageous to high integration.
FIG. 1A is a circuit diagram of memory cells included in a conventional NAND type flash memory. Referring to FIG. 1A, a conventional NAND type flash memory includes a plurality of word lines WL11-WL14, a plurality of memory cells M11-M14 that form a string structure with selective transistors ST1 and ST2 and that are connected to a bit line BL and a ground voltage VSS in series. Since the conventional NAND type flash memory uses a relatively small amount of cell current, a NAND type nonvolatile semiconductor memory device may perform a program with regard to all memory cells connected to one word line during one program operation.
FIG. 1B is a circuit diagram of memory cells included in a conventional NOR type flash memory. Referring to FIG. 1B, each of memory cells M21 through M26 are connected to bit lines BL1 and BL2 and a source line CSL in a NOR type nonvolatile semiconductor memory device. Since the conventional NOR type flash memory needs a relatively large amount of current consumption during a program operation, the NOR type flash memory may perform a program with regard to a specific number of memory cells during one program operation.
FIG. 2A is a graph illustrating a cell threshold voltage versus storage data when a flash memory device has a single level memory cell. FIG. 2B is a graph illustrating a cell threshold voltage versus storage data when a flash memory device has a multi level memory cell.
Referring to FIG. 2A, one bit data may be stored at two different threshold voltages when programmed in the single level memory cell. For example, when a threshold voltage between 1 to 3 volts (V) is programmed in the single level memory cell is, data logic “1” may be stored in the single level memory cell. When a threshold voltage between 5 to 7 volts is programmed in the single level memory cell, data logic “0” may be stored in the single level memory cell.
Referring to FIG. 2B, two bit data may be stored at four different threshold voltages when programmed in the multi level memory cell. For example, when a threshold voltage between 1 to 3 volts is programmed in the multi level memory cell, data logic “11” may be stored in the multi level memory cell. When a threshold voltage between 3.8 to 4.2 volts is programmed in the multi level memory cell, data logic “10” may be stored in the multi level memory cell. When a threshold voltage between 4.9 to 5.4 volts is programmed in the multi level memory cell, data logic “01” may be stored in the multi level memory cell. When a threshold voltage between 6.5 to 7.0 volts is programmed in the multi level memory cell, data logic “00” may be stored in the multi level memory cell.
Data stored in a single or multi level memory cell may be identified according to a difference in a cell current during a data read operation. The types of flash memories and operations thereof described above are well known to one of ordinary skill in the art and thus a detailed description has been omitted.
Hereinafter, a fluctuation of a read voltage according to a read while write function of a NOR type flash memory will now be described.
The NOR type flash memory may include a plurality of banks, with each bank including a plurality of nonvolatile memory cells. Each bank may share a data line for inputting and outputting data.
The NOR type flash memory may perform an erasure operation by sectors, and perform a program operation by a word or N words having consecutive addresses existing in one sector, where N is a real number.
To perform the program operation, the NOR type flash memory may receive a program instruction, receive a program address and program data to be programmed, temporarily store the program address and the program data in a buffer, select a memory cell corresponding to the program address, and apply a program voltage (or a write voltage) corresponding to the program data to the selected memory cell.
However, it is preferable that a NOR type flash memory for storing a code reduce the time delay period during a read operation.
Therefore, a method of generating and maintaining a voltage applied to a word line of a cell during a read operation in a standby status may be used to realize the above operation characteristic. In the standby status, a power voltage may be applied to a decoder of a flash memory. As a result, if a read instruction is applied to a NOR flash memory device, it may be possible to instantly perform a read operation without an operation delay time for generating a high read voltage.
However, operations of a NOR flash memory may be divided into a write operation for programming data and a read operation for reading the programmed data. It generally takes much longer time to perform the write operation than the read operation. For example, several tens of nanoseconds (ns) may be needed for the read operation, whereas several tens or hundreds of milliseconds (ms) may be needed for the write operation.
In order to reduce or prevent deterioration of overall performance of a NOR flash memory device due to the write operation being generally longer than the read operation, the NOR flash memory device may include an array having a plurality of banks and perform the write operation in one bank while performing the read operation in another of the banks, which may be commonly referred to as read while write (RWW).
Since a write voltage used to perform the write operation may differ from a read voltage used to perform the read operation, the NOR flash memory device may change the voltage applied to the decoder from the read voltage to the write voltage during the write operation and then perform the write operation. On the other hand, if the write operation precedes the read operation, the NOR flash memory device may change a voltage applied to the decoder from the write voltage to the read voltage to prepare for the instant read operation, in a manner similar to that described above.
Therefore, electrons may instantly move in order to fill in a capacitance existing in the decoder of an array where the write operation has completed and the read voltage follows. However, the read voltage may not remain constant and thus may drop.
FIG. 3 is a graph illustrating a fluctuation of a read voltage according to a RWW function of a conventional NOR flash memory device. In FIG. 3 Is shown a read voltage V1, a write voltage V2 and a control signal XSC. Referring to FIG. 3, the read voltage V1 drops (a circular dot line) at a point t1 where a write operation is changed to a read operation in response to the control signal XSC.
To address this problem, a size of an array, where a voltage is switched during the write operation, may be reduced, thereby reducing a voltage drop when the voltage is switched to the read voltage after the write operation is finished. However, it may be necessary to further reduce the fluctuation of the read voltage irrespective of the size of the array.